An analog-to-digital converter (ADC) is an important electronic building block that links real-world signals to the powerful capabilities of digital processing. Because analog signals may vary so widely over amplitude, frequency, and other requirements, a multitude of different ADC architectures have been developed. ADCs may be configured based on certain desired end-user application requirements, such as resolution, dynamic range, conversion rate, integral and differential linearity, power dissipation, accuracy, bandwidth, conversion delay, cost, package pin count, supply voltage range, or many other characteristics related to performance of the ADC. Desired end-user application requirements may be matched with an ADC's characteristics to achieve an appropriate conversion solution.
Different ADCs may be suitable for a particular problem set. For example, conventional flash ADCs may be relatively fast and therefore suitable for high-speed signals, such as in applications where the ADC is part of a high-speed closed loop system where small conversion delay is needed in the feedback path for digital processing and control. One disadvantage of conventional flash ADCs is that they may consume relatively high power. Additionally, conventional flash ADCs may be limited to bipolar junction transistor (BJT) technologies because of transistor mismatch errors, as will be explained herein. Because most conventional flash ADCs are based on BJT technology, the die size (i.e., footprint) of the conventional flash ADC may be relatively large and can be relatively expensive to manufacture.
Other ADC configurations may be suited for different applications. For example, successive-approximation ADCs operate by comparing the input voltage to the output of an internal digital-to-analog converter (DAC) until the best approximation is achieved. Successive-approximation ADCs may cure some of the deficiencies of the conventional flash ADC in that the successive-approximation ADC may be manufactured using advanced CMOS technologies, thus reducing the amount of silicon area consumed; however, the conversion rates for successive-approximation ADCs are an inverse function of resolution. Therefore, successive-approximation ADCs may not be suitable for applications that require fast conversion, but may be desirable for applications requiring small die size, for which conversion rate is of lesser importance.
Integrating ADCs apply an input voltage to the input of an integrator in order to ramp until the input integrator output returns to zero. Like the successive-approximation ADC, integrating ADCs can have high resolution, but are also relatively slow. However, one advantage of the integrating ADC is low power dissipation. Therefore, integrating ADCs may be desirable when low power dissipation is an important parameter, but conversion rate is not. Other ADC configurations exist that are not described herein, each configuration with advantages and disadvantages that may influence the selection of the ADC for a particular application. As an example, a configuration of a conventional flash ADC will be described for illustrative purposes.
FIG. 1 illustrates a simplified block diagram for a conventional flash analog-to-digital converter 100. Conventional flash ADC 100 includes a comparator string 110, a resistor string 120, and a decoder 130. Resistor string 120 includes individual resistors (R) connected in series between voltage references VREF1 and VREF2. The comparator string 110 includes individual comparators (Cp) in series in which one input to each individual comparator (Cp) of the comparator string 110 is operably coupled to an analog input signal VIN, and another input to each individual comparator (Cp) is operably coupled to intermediate voltage references located at nodes between the individual resistors (R) of the resistor string 120. Analog input signal VIN may simply be referred to herein as “VIN.” The outputs from each individual comparator (Cp) of the comparator string 110 are operably coupled to a decoder 130, which generates a digital output signal 135. Code block 125 is illustrated for ease of description and will be discussed later.
The number of resistors in the resistor string 120 is 2N, where “N” refers to the resolution (i.e., number of bits) of the ADC. The number of individual comparators (Cp) in the comparator string 110 is 2N−1. For example, a 6-bit flash ADC has 64 resistors and 63 comparators. Likewise, an 8-bit flash ADC has 256 resistors and 255 comparators, and so on. The intermediate voltage references between serially connected resistors, and input into one of the individual comparators (Cp) of the comparator string 110, are one less significant bit (LSB) greater than the reference voltage for the comparator below it. As used in the context of outputs (i.e., codes) and voltage references, LSB refers to the voltage references input into the comparator string 110, which translates into a corresponding code output from an individual comparator (Cp) of the comparator string 110. Later in this discussion, LSB may be referred to as a specific voltage level, which is intended to refer to the difference between adjacent voltage reference signals input into the comparator string 110.
In operation, when VIN is applied, each individual comparator (Cp) in the comparator string 110 compares VIN with the voltage reference signal corresponding to the particular individual comparator (Cp). If VIN increases to a level above the voltage level of the voltage reference signal of a particular individual comparator (Cp), then the output of the particular individual comparator (Cp) is asserted (e.g., 1). If VIN is at a voltage level below the voltage level of the voltage reference signal of a particular individual comparator (Cp), then the output of the particular comparator (Cp) is not asserted (e.g., 0). The code block 125 merely represents the state (e.g., asserted, not asserted) of the outputs (i.e., codes) of the individual comparators (Cp). While there may be additional circuitry or other components between the comparator string 110 and decoder 130, code block 125 itself should not be viewed as a physical component.
For this example, it is assumed that VREF1 is greater than VREF2, and that the intermediate voltage references between VREF1 and VREF2 decrease from VREF1 to VREF2 such that the outputs near the bottom of conventional flash ADC 100 are asserted first as VIN increases. The code block 125 may be thought of as the number of codes being asserted rises as voltage level of VIN increases, in a manner similar to a thermometer rising as temperature rises.
In FIG. 1, code block 125 illustrates the outputs from the bottom four individual comparators (Cp) to be asserted while the outputs from the top four individual comparators (Cp) are not asserted, indicating that VIN is at a voltage level greater than the voltage reference signals to the bottom four individual comparators (Cp) and lesser than the voltage reference signals to voltage reference signals to the top four individual comparators (Cp). The decoder 130 includes internal logic that converts the codes from the code block 125 into a digital output signal 135.
Individual comparators (Cp) in comparator string 110 of a conventional flash ADC 100 are generally configured using BJTs for reasons that will be discussed. A conventional flash ADC 100 may take advantage of BJTs comparatively good matching properties and relatively high transconductance for desirable comparator performance for certain applications. However, even the smallest BJTs may be relatively large (in comparison to other processes such as CMOS) and may consume considerable silicon area, thereby resulting in relatively large components and high manufacturing cost. Additionally, BJTs draw a parasitic base current through the resistor string 120 resulting in an accumulation of error that reduces accuracy. Designers may construct the resistor string 120 from metal such as aluminum, gold, or copper in an attempt to reduce the resulting error caused by this parasitic base current. However, a tradeoff may result as a low value resistance between VREF1 to VREF2 also results in high current flow through resistor string 120, and therefore may adversely contribute to power dissipation.
The combination of 2N BJT base terminals on a single VIN node also contributes to a large parasitic input capacitance. This parasitic input capacitance may be undesirable because a flash ADC is often used in high frequency applications. To achieve certain desired performance, BJTs may be biased with large bias current, which may range from approximately 100 microamps to several milliamps. For a successive-approximation ADC, where a single comparator is used over and over, such a large bias current may not result in significant problems; however, in a flash ADC, the parallel construction of the individual comparators (Cp) multiplies the large bias current by the resolution of the ADC. Because BJT performance drops when in saturation, the supply voltage range may be required to be sufficiently large enough for operation in the active region. This supply voltage (e.g., 5 V or higher) multiplied by the large bias current (e.g., 100s of mA) may result in an undesirably high power dissipation.
Despite the less desirable characteristics of the conventional flash ADC 100 discussed above, the flash ADC with BJTs remains the primary choice of designers for high frequency analog-to-digital conversion. Mere substitution of the BJTs in the comparators of comparator string 110 for sub-micron CMOS technology in a flash comparator may have relatively high speed, low power, low input capacitance, and low cost because of the smaller footprint; however, problems associated with transistor matching between CMOS transistors may be too great in comparison with matching between BJT transistors (see Table 1 below). The undesired mismatch may cause unacceptable differential non-linearity (DNL) errors. The DNL errors may be so large that entire codes may become missing or misplaced.
FIGS. 2A-2C show graphs illustrating various outputs 200, 225, 250 of a conventional flash analog-to-digital converter. For example, FIG. 2A illustrates an ideal output of a conventional flash ADC as VIN increases linearly from a low voltage to a high voltage. Codes 1 through “m” correspond to outputs of the comparator string, which are input into a decoder. FIG. 2B illustrates outputs of a conventional flash ADC as VIN increases linearly from a low voltage to a high voltage, in which one code (code j) experiences a DNL error. FIG. 2C illustrates outputs of a conventional flash ADC as VIN increases linearly from a low voltage to a high voltage, in which one code (code j) is missing or is misplaced. Each of the misbehaving bits may be a result of transistor mismatch from one of the many transistors of the conventional flash ADC (e.g., transistors in the comparators, load transistors, etc.). Because mismatch is greater in CMOS transistors in comparison to BJTs, these errors caused by the misbehaving bits illustrated by FIGS. 2B and 2C are more likely to occur.
FIGS. 3A and 3B illustrate configurations of comparators 300, 350, such as those used in a comparator string of a conventional flash analog-to-digital converter, using BJT and CMOS processes, respectively. FIG. 3A illustrates a comparator 300 according to a BJT process. FIG. 3B illustrates a comparator 350 according to a CMOS process. In both cases, the comparators 300, 350 are configured such that an output voltage at node VOUT is low when VIN is greater than VREF. However, the differences in comparators 300, 350 will be highlighted during the discussion below.
Those skilled in the art may be aware that increased gate area improves CMOS matching. For example, transistor matching in CMOS processes can be approximated by simplified Pelgrom's equations for variance (σ2(ΔP)) and standard deviation (σ(ΔP)) for a process parameter P (e.g., voltage) between two circuit elements:σ2(ΔP)≈AP2/WL→σ(ΔP)≈AP/√(WL)  (1).
Therefore, transistor matching is inversely proportional to the square root of gate area (WL). For improved transistor matching, the standard deviation σ(ΔP) should be minimized for improved DNL errors. However, improving transistor matching may cause degradation to conversion speed. In order to avoid degrading conversion speed, the following analysis guides the transistor design geometry.
Conversion speed (T) can be approximated by gate capacitance (C) multiplied by channel resistance (R). Gate capacitance is approximated as C≈εWL/tox. Channel resistance is approximated by R≈ρL/W. Therefore, conversion speed is T=RC≈ρL/W*εWL/tox=ρεL2/tox. Conversion speed may be written as:T≈βL2, where β=ρε/tox  (2).
Conversion speed (T) is, therefore, proportional to the square of the gate length (L) and is not a function of gate width (W). For the fastest speed, design goals may include minimizing the conversion speed (T) for high-speed operation by using the smallest possible gate length (L). Therefore, conversion speed and DNL can be managed independently. An improved (i.e., reduced) conversion speed (T) with a suitable DNL may be achieved by making gate length (L) small and gate width (W) large. Gate length (L) and width (W) can be independently chosen to improve both speed and matching. For example, an NMOS transistor may have a standard deviation of 30 mV for a 0.18 μm×0.8 μm gate in a CMOS process. A PMOS transistor may have a standard deviation of 40 mV for a 0.18 μm×0.8 μm gate in a CMOS process. A basic, conventional comparator used in a conventional flash ADC may have four NMOS and two PMOS transistors.σ=√(σn2+σn2+σn2+σn2σp2+σp2)=√[4(302)+2(402)]=82.5 mV  (3).
As a further example, 1 LSB may equal about 6 mV. In that case, a minimum geometry design such as the one listed above may produce 14 LSB code misplacements. As another example, 1 LSB=6 mV and the design goal is to reduce DNL (i.e., transistor matching, standard deviation) to be about ½ LSB (i.e., 3 mV). In this example, the required gate width (W) may be solved by Pelgrom's Equation for standard deviation:3 mV=σ=√[4AnP2/(WL)+2ApP2/(WL)]≈60/√W  (4).
AnP and ApP are the proportionality constants for the NMOS and PMOS transistors, respectively, and are assumed to be 10 mV and 12 mV, respectively in this example. It is noted that AnP and ApP are process and foundry dependent parameters; however, for the values given above are used in 0.18 μm CMOS processes, which is used as an example herein. Therefore, when solving for gate width (W), the gate width (W) is required to be approximately 400 μm wide for a ½ LSB DNL if the LSB is 6 mV for a conventional flash ADC using 0.18 μm gate length CMOS transistors. This transistor size is relatively very large and consumes a very large silicon area.
In other words, gate width (W) can be increased to improve comparator matching without degrading AC performance or decreasing the available linear range for combining adjacent comparator outputs. However, an increase in gate width (W) causes the current to proportionally increase to maintain the AC performance. For example, to maintain proper bias, each transistor may operate at a much higher operating current than a minimum geometry transistor (e.g., 0.18 μm×0.8 μm). Increasing the operating current may also increase the power dissipated by the conventional flash ADC by an undesirable amount. Thus, increasing gate width (W) to improve linearity has a power and die-size disadvantage. Consequently, a conventional flash ADC constructed using sub-micron CMOS transistors may be impractical.
Table 1, shows typical mismatch and DNL errors for different transistor types.
TABLE 1DNL Error w/6 mV Transistor TypeTypical MismatchLSBNPN - BJT<2mV⅓ LSBNMOS 0.18 μm × 0.8 μm30mV5LSBNMOS 1 μm × 1 μm9mV1.5LSBPMOS 0.18 μm × 0.8 μm40mV7LSBPMOS 1 μm × 1 μm12mV2LSB
In Table 1, it should be noted that 1σ matching when the LSB is 6 mV for the BJT design is about ⅓ LSB, while for the CMOS design 1σ matching may be as high as 7 LSBs. Given that an 8-bit converter has 255 parallel comparators, it may be reasonable to expect 3σ or higher variation, therefore a conventional flash ADC with 0.18 μm CMOS transistors may reasonably be expected have a few codes with greater than 21 LSBs of code misplacement error. Therefore, construction of a conventional flash ADC with sub-micron, minimum geometry CMOS transistors may not meet many application requirements.
Table 2 illustrates a side-to-side comparison between conventional BJT and CMOS flash ADC design. As seen in Table 2, BJTs have a lower standard deviation and DNL than a CMOS transistor. For this reason, and those described above regarding CMOS processes, BJT processes are generally used for conventional flash ADCs. However, as shown by Table 2, BJTs may have undesirable characteristics in comparison with CMOS including, higher power dissipation, larger silicon consumption and increased cost, and a lack of mixed signal monolithic capability.
TABLE 2ParameterBJTCMOSDNL2 mV30 mVPower DissipationHigh PowerLower PowerCostHigh CostLow CostConversion RateFastFastMixed Signal Monolithic CompatibilityNoYes
The inventor has appreciated that there exists a need for a method and apparatus for analog-to-digital conversion which may include one or more of the following parameters: relatively fast conversion rate, low conversion latency (i.e., propagation delay), low cost, low input bias current, low input capacitance and low power dissipation, which may improve upon some of the limitations of conventional ADCs, including conventional bipolar junction flash ADCs, successive-approximation ADCs and integrating ADCs.